1. Field of the Invention
The present invention generally relates to analog-to-digital conversion (ADC), and more particularly to automatically correcting a sampling clock phase or frequency in a digital system for performing ADC in a pixelated system.
2. Description of the Prior Art
When analog video signals are received and processed by a digital video system (also known as a pixelated system), such as a digital display or a graphics digitizer, the received analog video signals should be converted into a digital format before the signals are processed in digital domain. FIG. 1 is a block diagram illustrating an analog video source 10, such as a graphics card of a computer, and a digital video system 12, such as a liquid crystal display (LCD). The analog video source 10 provides analog video signals (e.g., analog RGB or YPbPr signals) to the digital video system 12 via a cable 14A. The received analog video signals are then converted into digital video signals by an analog-to-digital converter (ADC) 120. Along with the analog video signals are synchronization signals (e.g., a horizontal synchronization signal Hsyn and a vertical synchronization signal Vsyn) provided via a cable 14B. The received synchronization signals are processed by a clock generator 122 in order to generate a sampling clock (or pixel clock), which is used to trigger conversion by the ADC 120.
Due to varying impedances and lengths of the cables 14A and 14B, the analog video signals and the synchronization signals may arrive at the digital video system 12 at slightly different times. In other words, the phase or even the frequency of the sampling clock controlling the ADC 120 may not be acceptably synchronized with the phase/frequency of the pixel clock for generating the analog video signals in the analog video source 10. As a result, the quality of the processed output (such as the display image) of the digital video system 12 may be compromised.
In order to resolve such drawbacks in the conventional digital video system, schemes have been developed, such as disclosed, for example, in U.S. Pat. No. 5,767,916, entitled “Method and Apparatus for Automatic Pixel Clock Phase and Frequency Correction in Analog to Digital Video Signal Conversion.” This patent is directed to a technique of adjusting the pixel clock frequency by comparing the actual width of a video image with an expected image width. However, the technique may not accurately and effectively generate the pixel clock frequency in cases where the video image possesses substantial blank regions.
U.S. Pat. No. 6,268,848, entitled “Method and Apparatus Implemented in an Automatic Sampling Phase Control System for Digital Monitors,” discloses a technique of controlling sampling phase by collecting digital samples of a horizontal line, followed by finding the peak value and the valley value.
U.S. Patent Application No. 2006/0274207, entitled “Method and Apparatus for Analog Graphics Sample Clock Frequency Verification,” discloses a technique of automatically selecting the sampling frequency by measuring the difference between successive frames of images. However, the image data of an entire frame needs to be stored in order to measure the difference.
As a consequence of the above techniques not effectively or economically resolving the sampling clock phase/frequency problem, a need has arisen to propose a novel scheme that is capable of correcting sampling clock phase/frequency not only in an effective manner but also with minimum expenditure of resource and/or time.